A variety of logic schemes have been devised for counting purposes in the prior art, each method oriented toward accomplishing specific goals relating to input format, output format and speed. Binary weighted counting is most commonly used since if offers high efficiency in terms of the number of count states, 2.sup.b, that can be represented by a given number of bits or stages and construction is reasonably simple, however decoding individual count states is not particularly easy and most binary weighted counters exhibit discontinuities resulting from a combination of propagation delays and the frequent need for multiple bits to change simultaneously.
Discontinuities may be eliminated by use of a cyclic or Gray code in which only one bit changes state at a time, however this method tends to complicate both the counting scheme and the interpretation of its output. Another method of avoiding discontinuities is by use of a threshold format, which is not as efficient in terms of the number of count states, b+1, that can be represented by a given number of bits or stages, but offers simple output decoding and is suitable where a limited number of count states are needed. The threshold format is characterized by a linear series of outputs with all high logic states on one side of the threshold point and all low logic states on the opposite side and can progress one bit at a time from all low to all high as the threshold point advances. This format happens to be well suited to non-linear digital to analog conversion and various other applications.
Most counting schemes are designed to advance the output code only on half of the clock transitions, this poses a substantial limitation in certain applications where a higher resolution of the clock signal is needed. The resolution can be doubled by counting on both positive and negative transitions of the clock line, this is particularly useful with a symmetrical clock signal.